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Digital VLSI Circuits


  • 1:11:21 Mod-01 Lec-01 Introduction To Digital VLSI Design Flow

    Mod-01 Lec-01 Introduction To Digital VLSI Design Flow

    by Admin Added 18 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 55:36 Mod-05 Lec-02 Model Checking Algorithms I

    Mod-05 Lec-02 Model Checking Algorithms I

    by Admin Added 21 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:08:58 Mod-04 Lec-04 Syntax And Semantics Of CTL -- Continued

    Mod-04 Lec-04 Syntax And Semantics Of CTL -- Continued

    by Admin Added 42 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 59:46 Mod-11 Lec-01 Built In Self Test-1

    Mod-11 Lec-01 Built In Self Test-1

    by Admin Added 12 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:02:11 Mod-08 Lec-02 Fault Simulation-2

    Mod-08 Lec-02 Fault Simulation-2

    by Admin Added 48 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:23:50 Mod-03 Lec-03 Two Level Boolean Logic Synthesis-3

    Mod-03 Lec-03 Two Level Boolean Logic Synthesis-3

    by Admin Added 51 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:12:39 Mod-11 Lec-04 Memory Testing-2

    Mod-11 Lec-04 Memory Testing-2

    by Admin Added 21 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 57:13 Mod-07 Lec-03 Fault Equivalence

    Mod-07 Lec-03 Fault Equivalence

    by Admin Added 42 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 56:43 Mod-09 Lec-02 D-Algorithm-1

    Mod-09 Lec-02 D-Algorithm-1

    by Admin Added 41 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 53:09 Mod-04 Lec-01 Introduction To Formal Methods For Design Verification

    Mod-04 Lec-01 Introduction To Formal Methods For Design Verification

    by Admin Added 26 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:00:21 Mod-07 Lec-02 Functional And Structural Testing

    Mod-07 Lec-02 Functional And Structural Testing

    by Admin Added 17 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:07:01 Mod-02 Lec-04 Binding And Allocation Algorithms

    Mod-02 Lec-04 Binding And Allocation Algorithms

    by Admin Added 44 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 54:19 Mod-11 Lec-02 Built In Self Test-2

    Mod-11 Lec-02 Built In Self Test-2

    by Admin Added 11 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:08:10 Mod-08 Lec-03 Fault Simulation-3

    Mod-08 Lec-03 Fault Simulation-3

    by Admin Added 55 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 52:45 Mod-10 Lec-02 Scan Chain Based Sequential Circuit Testing-1

    Mod-10 Lec-02 Scan Chain Based Sequential Circuit Testing-1

    by Admin Added 25 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:08:11 Mod-03 Lec-01 Two Level Boolean Logic Synthesis-1

    Mod-03 Lec-01 Two Level Boolean Logic Synthesis-1

    by Admin Added 22 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 57:38 Mod-02 Lec-02 Scheduling Algorithms-1

    Mod-02 Lec-02 Scheduling Algorithms-1

    by Admin Added 42 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 54:46 Mod-07 Lec-01 Introduction To Digital VLSI Testing

    Mod-07 Lec-01 Introduction To Digital VLSI Testing

    by Admin Added 24 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 57:07 Mod-11 Lec-03 Memory Testing-1

    Mod-11 Lec-03 Memory Testing-1

    by Admin Added 21 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:02:56 Mod-05 Lec-01 Introduction To Model Checking

    Mod-05 Lec-01 Introduction To Model Checking

    by Admin Added 44 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:03:22 Mod-06 Lec-01 Binary Decision Diagram: Introduction And Construction

    Mod-06 Lec-01 Binary Decision Diagram: Introduction And Construction

    by Admin Added 15 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:04:16 Mod-03 Lec-02 Two Level Boolean Logic Synthesis-2

    Mod-03 Lec-02 Two Level Boolean Logic Synthesis-2

    by Admin Added 40 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 57:35 Mod-01 Lec-02 High Level Design Representation

    Mod-01 Lec-02 High Level Design Representation

    by Admin Added 28 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 56:45 Mod-05 Lec-03 Model Checking Algorithms II

    Mod-05 Lec-03 Model Checking Algorithms II

    by Admin Added 42 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

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