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Digital VLSI Circuits


  • 1:23:50 Mod-03 Lec-03 Two Level Boolean Logic Synthesis-3

    Mod-03 Lec-03 Two Level Boolean Logic Synthesis-3

    by Admin Added 42 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:10:10 Mod-02 Lec-03 Scheduling Algorithms-2

    Mod-02 Lec-03 Scheduling Algorithms-2

    by Admin Added 41 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:03:52 Mod-03 Lec-06 Multilevel Implementation

    Mod-03 Lec-06 Multilevel Implementation

    by Admin Added 46 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:00:53 Mod-06 Lec-03 Operation On Ordered Binary Decision Diagram

    Mod-06 Lec-03 Operation On Ordered Binary Decision Diagram

    by Admin Added 43 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 57:38 Mod-02 Lec-02 Scheduling Algorithms-1

    Mod-02 Lec-02 Scheduling Algorithms-1

    by Admin Added 33 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 56:43 Mod-09 Lec-02 D-Algorithm-1

    Mod-09 Lec-02 D-Algorithm-1

    by Admin Added 39 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:01:43 Mod-06 Lec-02 Ordered Binary Decision Diagram

    Mod-06 Lec-02 Ordered Binary Decision Diagram

    by Admin Added 44 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 52:25 Mod-08 Lec-01 Fault Simulation-1

    Mod-08 Lec-01 Fault Simulation-1

    by Admin Added 72 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 59:51 Mod-08 Lec-04 Testability Measures (SCOAP)

    Mod-08 Lec-04 Testability Measures (SCOAP)

    by Admin Added 71 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:02:56 Mod-05 Lec-01 Introduction To Model Checking

    Mod-05 Lec-01 Introduction To Model Checking

    by Admin Added 39 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:07:01 Mod-02 Lec-04 Binding And Allocation Algorithms

    Mod-02 Lec-04 Binding And Allocation Algorithms

    by Admin Added 57 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:08:58 Mod-04 Lec-04 Syntax And Semantics Of CTL -- Continued

    Mod-04 Lec-04 Syntax And Semantics Of CTL -- Continued

    by Admin Added 36 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:01:51 Mod-06 Lec-05 Symbolic Model Checking

    Mod-06 Lec-05 Symbolic Model Checking

    by Admin Added 53 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 57:37 Mod-01 Lec-03 Transformations For High Level Synthesis

    Mod-01 Lec-03 Transformations For High Level Synthesis

    by Admin Added 33 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:04:16 Mod-03 Lec-02 Two Level Boolean Logic Synthesis-2

    Mod-03 Lec-02 Two Level Boolean Logic Synthesis-2

    by Admin Added 41 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:08:10 Mod-08 Lec-03 Fault Simulation-3

    Mod-08 Lec-03 Fault Simulation-3

    by Admin Added 43 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:02:11 Mod-08 Lec-02 Fault Simulation-2

    Mod-08 Lec-02 Fault Simulation-2

    by Admin Added 41 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:01:16 Mod-02 Lec-01 Introduction To HLS: Scheduling, Allocation And Binding Problem

    Mod-02 Lec-01 Introduction To HLS: Scheduling, Allocation And Binding Problem

    by Admin Added 44 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 57:27 Mod-05 Lec-04 Model Checking With Fairness

    Mod-05 Lec-04 Model Checking With Fairness

    by Admin Added 51 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 56:45 Mod-05 Lec-03 Model Checking Algorithms II

    Mod-05 Lec-03 Model Checking Algorithms II

    by Admin Added 33 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:08:11 Mod-03 Lec-01 Two Level Boolean Logic Synthesis-1

    Mod-03 Lec-01 Two Level Boolean Logic Synthesis-1

    by Admin Added 31 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 57:13 Mod-07 Lec-03 Fault Equivalence

    Mod-07 Lec-03 Fault Equivalence

    by Admin Added 35 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 1:16:37 Mod-03 Lec-04 Heuristic Minimization Of Two-Level Circuits

    Mod-03 Lec-04 Heuristic Minimization Of Two-Level Circuits

    by Admin Added 33 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

  • 55:20 Mod-04 Lec-02 Temporal Logic: Introduction And Basic Operators

    Mod-04 Lec-02 Temporal Logic: Introduction And Basic Operators

    by Admin Added 28 Views / 0 Likes

    Design Verification and Test of Digital VLSI Circuits by Prof. Jatindra Kumar Deka, Dr. Santosh Biswas, Department of Computer Science and Engineering, IIT G...

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